1. Field of the Invention
The present invention relates to an operational amplifier, and more particularly, to an operational amplifier suited for use in portable communication equipment and the like.
2. Description of the Related Art
Japanese Unexamined Patent Publication No. 7-46059 shows a conventional operational amplifier (see FIG. 3). Referring to FIG. 3, an operational amplifier 100 comprises a differential amplifier stage 1, a current mirror stage 2, and a buffer circuit 3. The differential amplifier stage 1 includes first and second differential amplifier circuits 1a, 1b, respectively, arranged symmetrically with respect to a transverse center line of the circuit. The current mirror stage 2 comprises first and second current mirror circuits 2a, 2b, respectively, arranged symmetrically with respect to a transverse center line of the circuit. The buffer circuit 3 is connected to the common output of the current mirror circuits 2a, 2b.
The first differential amplifier circuit 1a is formed of a pair of NPN transistors Q1, Q2. The second differential amplifier circuit 1b is formed of a pair of PNP transistors Q3, Q4. The first current mirror circuit 2a comprises three PNP transistors Q5, Q6, and Q7. The second current mirror circuit 2b is made up of three NPN transistors Q8, Q9, and Q10. The buffer circuit 3 has a diamond arrangement, and includes two NPN transistors Q11, Q13, and two PNP transistors Q12, Q14. The buffer circuit is also provided with a PNP transistor Q15 and an NPN transistor Q16 which act as current sources. Transistors Q11, Q12 are first and second input transistors, respectively, and transistors Q13, Q14 are first and second output transistors, respectively.
In the above arrangement, the bases of transistors Q1, Q3 (which are taken from the first and second differential amplifier circuits 1a, 1b, respectively) are connected to a positive-phase input terminal IN1. The bases of the remaining transistors Q2, Q4, are connected to a negative-phase input terminal IN2. The collector of transistor Q1 is the output of the first differential amplifier circuit 1a, and is connected to the input of the first current mirror circuit 2a. The collector of transistor Q2 is connected to a positive power source +Vcc. The emitters of transistors Q1, Q2 are directly tied together and are connected to a first constant current circuit 4a. Further, the collector of transistor Q3 is the output of the second differential amplifier circuit 1b, and is connected to the input of the second current mirror circuit 2b. The collector of transistor Q4 is connected to a negative power source -Vcc. The emitters of transistors Q3, Q4 are directly tied together and are connected to a second constant current circuit 4b. The collectors of transistors Q7, Q10 (which are the outputs of the first and second current mirror circuits 2a, 2b, respectively) are connected to the positive and negative power sources +Vcc, -Vcc, respectively through respective phase compensating capacitors C1, C2. In addition, the collectors of transistors Q7 and Q10 are directly tied together and connected to the input of the buffer circuit 3.
In the buffer circuit 3, transistors Q15, Q16 are used as current sources for transistors Q11, Q12, respectively. More particularly, the collector of transistor Q15 is connected to a node between the emitter of transistor Q12 and the base of transistor Q13. The emitter of transistor Q15 is connected to the positive voltage +Vcc, and the base of transistor Q15 is connected to the bases of transistors Q5, Q6 (which are directly tied together) in the second current mirror circuit 2a. The collector of transistor Q16 is connected to a node between the emitter of transistor Q11 and the base of transistor Q14. The emitter of transistor Q16 is connected to the negative voltage -Vcc, and the base of transistor Q16 is connected to the bases of transistors Q8, Q9 (which are directly tied together) in the current mirror circuit 2b. Thus, the buffer circuit 3 is controlled with the operating current flowing in the current mirror stage 2, depending on an input signal voltage.
For the operational amplifier 100 described above to operate at a high speed and over a wide bandwidth, it is necessary to increase the mutual conductance of the differential amplifier stage 1 (i.e., converting a voltage in a current). To increase the mutual conductance of the differential amplifier stage 1, one must increase a current flowing in the differential amplifier stage 1.
In the above-described arrangement of the conventional operational amplifier 100, the increase of current flowing in the differential amplifier stage 1 is accomplished by enhancing the increasing change-ratio of current flowing in the first current mirror circuit 2a of the current mirror stage 2, and enhancing the decreasing change-ratio of current flowing in the second current mirror circuit 2b. As a result, the increasing change-ratio of the current in the first current mirror circuit 2a cannot be processed in the buffer circuit 3. The current which cannot be processed in the buffer circuit 3 begins to flow into the second current mirror circuit 2b in which the current is reduced. Accordingly, the second current mirror circuit 2b becomes saturated and cannot normally operate.